The general structures and manufacturing processes for electronic packages are described in, for example, Donald P. Seraphim, Ronald Lasky, and Che-Yo Li, Principles of Electronic Packaging, McGraw-Hill Book Company, New York, N.Y., (1988), and Rao R. Tummala and Eugene J. Rymaszewski, Microelectronic Packaging Handbook, Van Nostrand Reinhold, New York, N.Y. (1988), both of which are hereby incorporated herein by reference.
As described by Seraphim et al., and Tummala et al., an electronic circuit contains many individual electronic circuit components, e.g., thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components are interconnected to form the circuits, and the individual circuits are interconnected to form functional units. Power and signal distribution are done through these interconnections. The individual functional units require mechanical support and structural protection. The electrical circuits require electrical energy to function, and the removal of thermal energy to remain functional. Microelectronic packages, such as, chips, modules, circuit cards, and circuit boards, are used to protect, house, cool, and interconnect circuit components and circuits.
Within a single integrated circuit, circuit component to circuit component and circuit to circuit interconnection, heat dissipation, and mechanical protection are provided by an integrated circuit chip. This chip is referred to as the "zeroth" order package, while the chip enclosed within its module is referred to as the first level of packaging.
There is at least one further level of packaging. The second level of packaging is the circuit card. A circuit card performs at least four functions. First, the circuit card is employed because the total required circuit or bit count to perform a desired function exceeds the bit count of the first level package, i.e., the chip. Second, the second level package, i.e., the circuit card, provides a site for components that are not readily integrated into the first level package, i.e., the chip or module. These components include, e.g., capacitors, precision resistors, inductors, electromechanical switches, optical couplers, and the like. Third, the circuit card provides for signal interconnection with other circuit elements. Fourth, the second level package provides for thermal management, i.e., heat dissipation.
In most applications, and especially personal computers, high performance workstations, mid range computers, and main frame computers, there is a third level of packaging. This is the board level package. The board contains connectors to accept a plurality of cards, circuitization to provide communication between the cards, I/O devices to provide external communication, and, frequently, sophisticated thermal management systems.
Many cards and boards, and especially those having a large number of I/O leads, and high wiring density, are multi-layer packages. Multi-layer packages have a plurality of signal planes, at least one power plane, and at least one ground plane.
The structural unit of the multi-layer package is the "core." The core is a composite structure of either ceramic or "pre-preg" between sheets of copper foil. "Pre-preg" is formed by impregnating fiber, for example, glass fiber or polytetrafluoroethylene fiber, with a resin, for example an epoxy resin or a polyimide resin, evaporating the solvents, and partially curing the resin to a "B-stage." A "core" is formed by laminating several plies of "pre-preg" between a pair of treated copper foil sheets. Lamination is carried out at elevated temperatures and pressures, to fuse and cure the resin.
The cores are "circuitized" by photolithographic processing of the copper foil. In the case of "subtractive" circuitization the "core" is drilled (for vias and through holes), seeded, and plated. Resist is then applied to the surface, and exposed and developed. The copper that is uncovered is then etched away, leaving behind the circuitization.
In the "additive" circuitization process, which is especially preferred for fine lines and high wiring densities, the core is drilled, and the copper then etched away. Thereafter photoresist is applied to the bare dielectric laminate, exposed in areas not desired for circuitry, and developed. In the development process the unexposed resist is removed, leaving channels in the resist layer. Copper circuitization is plated into these channels, for example, by electroless copper plating.
Multilayer microelectronic packages contain many interleaved layers of dielectric and circuitization. Superficially, the composite printed circuit package is fabricated by interleaving cores (including signal cores, signal/signal cores, power cores, power/power cores, and signal/power cores) with additional sheets of prepreg, and surface circuitization. However, throughout the fabrication process the individual "cores" are registered, imaged, etched, drilled, registered again, aligned with other layers, and ultimately laminated to those other layers. It is only after all of the hole drilling, photolithography, plating and alignment/registration processes are successfully repeated within specification many times and lamination is completed that a multilayer composite is finally obtained.
Successful repetition of first registration, imaging, etching, drilling, second registration, and alignment, and lamination is required by the demands of denser circuitry, increased numbers of layers, finer circuit line tracks, narrower dielectric layers, narrower circuitization layers, and smaller diameter through holes and vias. These requirements translate into a requirement for highly accurate feature generation registration and lamination alignment and registration. Poor registration, whether at the feature generation stage or at the lamination stage, will consume the tolerance available for subsequent procedures, such as lay-up, and subsequent lamination, or registration.
One method of aligning layers of multi-layer printed circuit boards is by the use of so called "alignment holes" in the periphery of the layer. These holes are located and drilled as part of the same process as the vias and through holes, and are then aligned with alignment pins. Examples of registration utilizing alignment holes and pins are described most recently, for example, in U.S. Pat. No. 4,829,375 to Donald Alzmann, Michael Angelo, Paul Waldner, and Arthur Brady for METHOD FOR PUNCHING IN PRINTED CIRCUIT BOARD LAMINATES AND RELATED APPARATUS AND ARTICLES OF MANUFACTURE, U.S. Pat. No. 4,568,971 to Donald Alzmann, Michael Angelo, and Paul Waldner for METHOD AND APPARATUS FOR SUCCESSIVELY POSITIONING SHEETS OF MATERIAL WITH PRECISION FOR PUNCHING ALIGNING HOLES IN THE SHEETS ENABLING THE SHEETS TO BE USED IN THE MANUFACTURE OF COMPOSITE CIRCUIT BOARDS, and U.S. Pat. No. 4,481,533 to Donald Alzmann, Michael Angelo, and Paul Waldner for METHOD AND APPARATUS FOR SUCCESSIVELY POSITIONING SHEETS OF MATERIAL WITH PRECISION FOR PUNCHING ALIGNING HOLES IN THE SHEETS ENABLING THE SHEETS TO BE USED IN THE MANUFACTURE OF COMPOSITE CIRCUIT BOARDS, and M. Angelo, "Multilayer Registration Tooling--The Full Spectrum", Printed Circuit Fabrication, 10, (7), pp. 24-25, 27-30, and 33-34 (July 1987).
As described in these documents the registration of a layer in a multi-layer module is effected by drilling of "alignment holes" in the layers. Once these "alignment holes" are drilled, an "alignment post" is inserted in and extends outwardly from each "alignment hole" of the first layer. This "alignment post" is then used to align the both photomask art work and subsequent layers.
The aforementioned U.S. Pat. Nos. 4,829,375, 4,568,971 and 4,481,533 describe various means of locating holes, including the "alignment holes." U.S. Pat. No. 4,481,533 to Donald Alzmann, Michael Angelo, and Paul Waldner for METHOD AND APPARATUS FOR SUCCESSIVELY POSITIONING SHEETS OF MATERIAL WITH PRECISION FOR PUNCHING ALIGNING HOLES IN THE SHEETS ENABLING THE SHEETS TO BE USED IN THE MANUFACTURE OF COMPOSITE CIRCUIT BOARDS, describes apparatus, including an imaging system, for effecting operations at precise sites on the layers of a multilayer printed circuit board. The individual layers are held in place and imaged by the imaging system to detect reference markings on the layer. The imaging system also includes means for generating an index marking which is algorithmically related to the reference markings. These index markings are then used to position a tool for carrying out operations on the sheets. The operations include hole forming, for example "alignment holes."
U.S. Pat. No. 4,568,971 to Donald Alzmann, Michael Angelo, and Paul Waldner for METHOD AND APPARATUS FOR SUCCESSIVELY POSITIONING SHEETS OF MATERIAL WITH PRECISION FOR PUNCHING ALIGNING HOLES IN THE SHEETS ENABLING THE SHEETS TO BE USED IN THE MANUFACTURE OF COMPOSITE CIRCUIT BOARDS specifically describes method and apparatus for forming holes in the individual layers of multilayer printed circuit boards. The described method includes moving the layer to bring reference marks on the surface of a reference sheet into coincidence with index marks in an imaging system. After coincidence, the reference sheet is removed, and the sheet in which the hole is to punched is substituted for the reference sheet.
U.S. Pat. No. 4,829,375 to Donald Alzmann, Michael Angelo, Paul Waldner, and Arthur Brady for METHOD FOR PUNCHING IN PRINTED CIRCUIT BOARD LAMINATES AND RELATED APPARATUS AND ARTICLES OF MANUFACTURE, describes an optical coincidence method of locating and employing a tool to treat a substrate. In the described method a pattern and a target are located in prescribed relationship on the substrate. The substrate is then positioned on a carrier, and the location of the target is determined by means of an imaging system. The imaging system generates a location reference relative to the tool, a location of the target reference, and an error signal. The error signal then drives the movement of the target and the substrate into relationship with the location reference so that the substrate is in a prescribed relationship with the tool. The tool, now properly located, performs an operation on the substrate, for example, punching. The tool is disclosed to pierce the tooling configuration into the substrate. This hole forming tooling configuration can be used in subsequent production steps, described as lamination and drilling, to ensure layer-to-layer and image-to-drill registration.
To be noted is that these documents still require alignment holes and alignment posts to align and register one sheet of a multilayer package with another sheet of the package.
Other United States Patents describe optical systems for processing layers. For example, U.S. Pat. No. 4,203,132 to A. Schmitt, K. Schafer, and D. Utz for METHOD OF ALIGNMENT describes a method of aligning two parts by imaging at least two points on each of the parts to be aligned. The points have a separation that is less then the tolerance in positioning the parts. The points are then moved into prescribed position to align the two parts.
U.S. Pat. No. 4,404,741 to J. Lebet, L. Peterle, and F. Matthey-Doret for DEVICE FOR ALIGNMENT OF A PART AND A SUBSTRATE FOR CARRYING THE PART describes a mechanical assembly station for alignment of a part and a substrate by direct optical observation of features on the two bodies.
U.S. Pat. No. 4,494,139 to Y. Shima, S. Kashioka, T. Uno, and K. Suzuki for AUTOMATIC ASSEMBLY SYSTEM describes an alternative mechanical assembly station for alignment of a part and a substrate by direct optical observation of features on the two bodies, and the generation of an error function based upon the separation of body features.
U.S. Pat. No. 4,655,600 to Tanigawa for ALIGNMENT METHOD describes a method of alignment where "V" shaped marks are provided on the bodies to be aligned. Straight line reference marks are used to determine the positions of the "V" shaped marks, and to thereby generate an error signal that aligns the bodies.
U.S. Pat. No. 4,663,658 to M. Lanne, G. Pons, J. Petit, and F. Pauly for PROCESS AND DEVICE FOR ASSISTING THE POSITIONING OF WORKPIECES BY SUPERPOSITIONING OF IMAGES describes a positioning method and system where an image of the workpiece is displayed, along with a test pattern, on the screen of an imaging system. According to Lanne et al the workpiece has an image of this test pattern on its surface. The workpiece is moved until the virtual test pattern is brought into coincidence with the actual test pattern on the surface of the workpiece.
U.S. Pat. No. 4,680,627 for A. Sase, T. Nagata, M. Fukunaga, and Y. Satomi for APPARATUS FOR CHECKING PATTERNS ON PRINTED CIRCUIT BOARDS describes an alignment system that matches alignment marks on the workpieces.
U.S. Pat. No. 4,731,923 to H. Yagi, S. Tando, and T. Nakamura for APPARATUS AND METHOD FOR MOUNTING CIRCUIT ELEMENT ON PRINTED CIRCUIT BOARD describes an alignment system that align features of the workpieces with each other.
The above described United States Patents all describe the use of a feature on one workpiece to align that workpiece with another workpiece. However, for registration and alignment of successive layers in a multi-layer microelectronic package, layer to layer alignment of successive features builds up an alignment error that is the statistical sum of the individual errors on each layer. This results in a severe alignment-limited yield.